1. Technical Field
Embodiments described herein are related to the field of integrated circuit implementation, and more particularly to the implementation of memory power management.
2. Description of the Related Art
Semiconductor manufacturing technologies continue to reduce scale allowing for smaller geometries and feature sizes, and System-on-a-Chip (SoC) designs utilize these newer technologies to increase performance and/or reduce power consumption. These scaled technologies, however, present some design challenges. One challenge may be reliable operation of memory cells.
Static memory cells operate by latching a state, commonly referred to as a “1” or “0” or as a “high” or “low” within a small circuit. A memory cell may actually store two values, one representing the data value stored in the memory cell and the other value being the opposite of the data value, i.e., the inverse of the data value. A write to a memory cell that changes the data value may require forcing the stored values to opposite states. In other words, to change a memory cell from a high to a low, the data value currently in a high state may be driven to a low state and the inverse data value currently in a low state may be driven high. For the write operation to be successful, the driven values must force the circuit of the memory cell to swap states, thereby storing the low value in the data value and the high value in the inverse data value.
As semiconductor technologies shrink, the ability to write to memory cells and force the states to swap becomes more difficult. A method of improving the reliability of writing to memory cells created in the smaller geometries is desired.